ELECTRICALLY ISOLATED GATE CONTACT IN FINFET TECHNOLOGY FOR CAMOUFLAGING INTEGRATED CIRCUITS FROM REVERSE ENGINEERING

A system and method for adding a source contact, a drain contact, and an apparent gate contact to a FinFET having a fin including a source region, a drain region, and a gate disposed over the fin forming one or more transistor junctions with the fin. The method comprises producing a source contact o...

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Bibliographic Details
Main Authors Chow, Lap Wai, Wang, Bryan J, Cocchi, Ronald P, Baukus, James P
Format Patent
LanguageEnglish
Published 12.08.2021
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A system and method for adding a source contact, a drain contact, and an apparent gate contact to a FinFET having a fin including a source region, a drain region, and a gate disposed over the fin forming one or more transistor junctions with the fin. The method comprises producing a source contact opening extending downward to a first region electrically coupled to the source region, a drain contact opening extending downward to a second region electrically coupled to the drain region, and a gate contact opening extending downward to a third region electrically isolated from the gate, and filling the source contact opening, the drain contact opening, and the gate contact opening with a conductive metal.
Bibliography:Application Number: US202117157567