AVOIDING PROCESSOR STALL WHEN ACCESSING COHERENT MEMORY DEVICE IN LOW POWER

A memory subsystem with memory managed with coherent access can manage page table entries to enable putting the memory in a low power state. The memory control can change a page table entry for the memory prior to triggering the memory to enter the low power state. The change to the page table entry...

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Bibliographic Details
Main Authors BOYD, James A, COX, Christopher E, TALPALLIKAR, Nikhil
Format Patent
LanguageEnglish
Published 29.07.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A memory subsystem with memory managed with coherent access can manage page table entries to enable putting the memory in a low power state. The memory control can change a page table entry for the memory prior to triggering the memory to enter the low power state. The change to the page table entry will cause a page fault for a subsequent access to the memory. The page fault will trigger handling the access to the memory with a fault routine, avoiding synchronous delay to the memory that would occur with normal access.
Bibliography:Application Number: US202117227220