POWER DELIVERY TIMING FOR MEMORY

A system can comprise a memory device and sequencing circuitry configured to provide enable signals to a number of voltage regulators in association with providing sequenced power signals to the memory device. The system can include voltage threshold detection circuitry configured to: detect primary...

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Bibliographic Details
Main Authors Benjamin, Keith A, Dougherty, Thomas
Format Patent
LanguageEnglish
Published 01.07.2021
Subjects
CALCULATING
COMPUTING
CONTROL OR REGULATING SYSTEMS IN GENERAL
CONTROLLING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
FUNCTIONAL ELEMENTS OF SUCH SYSTEMS
INFORMATION STORAGE
MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS
PHYSICS
REGULATING
STATIC STORES
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Summary:A system can comprise a memory device and sequencing circuitry configured to provide enable signals to a number of voltage regulators in association with providing sequenced power signals to the memory device. The system can include voltage threshold detection circuitry configured to: detect primary supply voltage events; and responsive to detecting a primary supply voltage event, deassert a timer enable signal provided to timing circuitry. The timing circuitry is configured to, responsive to the deassertion of the timer enable signal: deassert a primary enable signal provided to the sequencing circuitry; and maintain the primary enable signal in a deasserted state for a particular amount of time prior to reasserting the primary enable signal.
Bibliography:Application Number: US202017126651