SYSTEMS AND METHODS FOR MAPPING MATRIX CALCULATIONS TO A MATRIX MULTIPLY ACCELERATOR

Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the o...

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Bibliographic Details
Main Authors Henry, Michael, Fick, Laura, Akrzyniarz, Skylar, Morten, Andrew, Johnson, Scott, Parikh, Malav, Fick, David, Wu, Pei-Ci
Format Patent
LanguageEnglish
Published 24.06.2021
Subjects
CALCULATING
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.
Bibliography:Application Number: US202117193339