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A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and sto...

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Bibliographic Details
Main Authors SALZ, Arturo, Chou, Ching-Ping, Vidal, Luc Francois, Colrat, Jean-Philippe, Mbotchak, Arnold, Delerse, Sebastien Roger
Format Patent
LanguageEnglish
Published 20.05.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.
Bibliography:Application Number: US202117161574