INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM

A method of generating a netlist of an IC device includes receiving gate region information of the IC device. The gate region information includes a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, a location of a gat...

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Bibliographic Details
Main Authors CHANG, Lester, LAI, Wen-Koi, HO, Jon-Hsu, WU, Ze-Ming, LU, KuoPei, SU, Ke-Wei, HSIEH, Wen-Hsing, SU, Ke-Ying, KUO, Keng-Hua, CHEN, Liang-Yi
Format Patent
LanguageEnglish
Published 11.03.2021
Subjects
APPARATUS SPECIALLY ADAPTED THEREFOR
CALCULATING
CINEMATOGRAPHY
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTROGRAPHY
HOLOGRAPHY
MATERIALS THEREFOR
ORIGINALS THEREFOR
PHOTOGRAPHY
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES
PHYSICS
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Summary:A method of generating a netlist of an IC device includes receiving gate region information of the IC device. The gate region information includes a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, a location of a gate via positioned within the active region and along the width, and a first gate resistance value corresponding to the gate region. The method includes determining a second gate resistance value based on the location and the width, and modifying the netlist based on the second gate resistance value.
Bibliography:Application Number: US202016950999