METAL LAYER PATTERNING FOR MINIMIZING MECHANICAL STRESS IN INTEGRATED CIRCUIT PACKAGES

A method may include forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between th...

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Bibliographic Details
Main Authors HOLLAND, Kathryn Rose, PANG, Yaoyu, TARABBIA, Marc L, BARR, Alexander
Format Patent
LanguageEnglish
Published 04.03.2021
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method may include forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between the inner shape and the outer field and approximately centering the void space on an outline of an under-bump metal formed under the target bump with a keepout distance from the inner shape and the outer field on either side of the outline such that the metal minimizes local variations in mechanical stress on underlying structures within the fabricated integrated circuit device.
Bibliography:Application Number: US202016897036