INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM

A method of generating an integrated circuit (IC) layout diagram of an IC device includes receiving the IC layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region. The width is divided into a plurality of width segments based on a locatio...

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Bibliographic Details
Main Authors CHANG, Lester, SU, Ke-Wei, SU, Ke-Ying, KUO, Keng-Hua
Format Patent
LanguageEnglish
Published 21.01.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method of generating an integrated circuit (IC) layout diagram of an IC device includes receiving the IC layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region. The width is divided into a plurality of width segments based on a location of a gate via, and a simulation is performed based on the IC layout diagram and including an effective resistance calculated using at least one width segment of the plurality of width segments.
Bibliography:Application Number: US202017031610