DIELECTRIC MOLDED INDIUM BUMP FORMATION AND INP PLANARIZATION

• Main Authors: Ettenberg, Martin H, Lange, Michael
• Format: Patent
• Language: English
• Published: 31.12.2020
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The disclosed technique may be used to electrically and physically connect semiconductor wafers to allow high density interconnects and accommodate mismatched coefficients of thermal expansion materials by having room temperature hybridization as well as to remove the bow from wafers. The wafers may utilize a thick dielectric to remove the bow and create a planar surface. Indium bumps may be deposited and patterned in a dielectric film with a small diameter, tall height and substantially uniform in size and shape. The indium can be melted to create small grain size and uniform height bumps. The dielectric film may feature trenches around the indium bumps to prevent shorting of pixels when pressed together. The small size of the columns enables wafer or chip scale hybridization with a very high interconnect density, high reliability, and the ability to accommodate mismatches in the coefficients of thermal expansion of the constituent materials.