SEMICONDUCTOR DEVICES HAVING PAD ISOLATION PATTERN

A semiconductor device is described which includes a substrate, an interlayer insulating layer provided below the substrate and including a via pad therein, a through via located at least partially within a via hole passing through the substrate and a portion of the interlayer insulating layer, a co...

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Bibliographic Details
Main Authors JEON, JINJU, CHOI, YOUNGHWAN, PARK, BYUNGJUN
Format Patent
LanguageEnglish
Published 05.11.2020
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A semiconductor device is described which includes a substrate, an interlayer insulating layer provided below the substrate and including a via pad therein, a through via located at least partially within a via hole passing through the substrate and a portion of the interlayer insulating layer, a connection pad on the substrate, and a pad isolation pattern formed in the substrate to be located around the connection pad and the through via. The pad isolation pattern includes a plurality of bent portions having protrusions and recesses when viewed from a top view. As a result, cracks may be prevented from forming or growing in the semiconductor device.
Bibliography:Application Number: US201916580024