ELECTRICAL FUSE FORMATION DURING A MULTIPLE PATTERNING PROCESS

Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to conne...

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Bibliographic Details
Main Authors Chae, Moosung M, Zang, Hui, Zhang, Xiaoqiang, Yin, Haizhou, Liu, Jinping, Shu, Jiehui
Format Patent
LanguageEnglish
Published 22.10.2020
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.
Bibliography:Application Number: US202016918053