Chip to Lead Interconnect in Encapsulant of Molded Semiconductor Package

• Main Authors: Chiang, Chau Fatt, Saw, Khay Chwan
• Format: Patent
• Language: English
• Published: 08.10.2020
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A semiconductor package includes an electrically insulating first encapsulant body having an upper surface, a first semiconductor die encapsulated within the first encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the first encapsulant body, a plurality of electrically conductive leads, each of the leads having interior ends that are encapsulated within the first encapsulant body and outer ends that are exposed from the first encapsulant body, and a first direct electrical connection between the first conductive pad and the interior end of a first lead from the plurality. The first direct electrical connection includes a first conductive track formed in the upper surface of the first encapsulant body. The first encapsulant body includes a laser activatable mold compound. The first conductive track is formed in a first laser activated region of the laser activatable mold compound.