FAILURE MODE STUDY BASED ERROR CORRECTION

A method for error correction in a memory system includes determining a bit error ratio for a memory block of the memory system during a read operation. The method further includes determining whether the bit error ratio is between a first threshold and a second threshold. The method further include...

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Bibliographic Details
Main Authors CR, Narendhiran, Jayaraman, Muralitharan, Rajendran, Balakumar, Amarnath, Abhinand, Kumari, Indu
Format Patent
LanguageEnglish
Published 03.09.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A method for error correction in a memory system includes determining a bit error ratio for a memory block of the memory system during a read operation. The method further includes determining whether the bit error ratio is between a first threshold and a second threshold. The method further includes based on a determination that the bit error ratio is between the first threshold and the second threshold, performing a select gate drain (SGD) read operation on a SGD word line of the memory block. The method further includes generating first soft bit data using SGD data corresponding to the SGD read operation. The method further includes performing a low-density parity-check correction using the first soft bit data on the memory block.
Bibliography:Application Number: US201916289738