Semiconductor Memory Device Having an Electrically Floating Body Transistor

An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a bur...

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Bibliographic Details
Main Authors Or-Bach, Zvi, Widjaja, Yuniarto
Format Patent
LanguageEnglish
Published 30.07.2020
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.
Bibliography:Application Number: US202016844715