METHOD OF FABRICATING A PLURALITY OF LINEAR ARRAYS WITH SUBMICRON Y-AXIS ALIGNMENT

• Main Authors: Redding, Gary D, Casey, Joseph F
• Format: Patent
• Language: English
• Published: 16.07.2020
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method of assembling a plurality of linear arrays from a silicon wafer having a first surface and a second surface opposite the first surface, the first surface having at least a first linear array of sensor/emitter elements and a second linear array of sensor/emitter elements, each arranged parallel relative to a first direction, and a sacrificial portion positioned between the first linear array of sensor/emitter elements and the second linear array of sensor/emitter elements. The method includes: forming a first cavity in the second surface positioned opposite the sacrificial portion and parallel relative to the first direction; forming at least a first through cut, a second through cut, a third through cut and a fourth through cut in the silicon wafer, the first and second through cuts are parallel to the first direction, the third and fourth through cuts are perpendicular to the first direction, the first through cut arranged adjacent to the first linear array of sensor/emitter elements opposite the sacrificial portion, the second through cut arranged adjacent to the second linear array of sensor/emitter elements opposite the sacrificial portion, and the third and fourth through cuts form a first end and a second end, respectively, of a multi-row sensor/emitter chip defined by the first, second, third and fourth through cuts; bonding at least a portion of the multi-row sensor/emitter chip formed by the second surface of the silicon wafer to a mounting substrate; and, removing the sacrificial portion.