SYNCHRONOUS DEVICE WITH SLACK GUARD CIRCUIT

The present disclosure relates to a synchronous device comprising: a first latch (206) having a data input receiving a data input signal (LD1) and configured to store the data input signal (LD1) during a first state of a first clock signal (CP′); and a slack guard circuit comprising: a delay element...

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Bibliographic Details
Main Authors LOUVAT, Mathieu, JURE, Lionel, HUARD, Vincent
Format Patent
LanguageEnglish
Published 25.06.2020
Subjects
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