SYNCHRONOUS DEVICE WITH SLACK GUARD CIRCUIT

The present disclosure relates to a synchronous device comprising: a first latch (206) having a data input receiving a data input signal (LD1) and configured to store the data input signal (LD1) during a first state of a first clock signal (CP′); and a slack guard circuit comprising: a delay element...

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Bibliographic Details
Main Authors LOUVAT, Mathieu, JURE, Lionel, HUARD, Vincent
Format Patent
LanguageEnglish
Published 25.06.2020
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PULSE TECHNIQUE
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Summary:The present disclosure relates to a synchronous device comprising: a first latch (206) having a data input receiving a data input signal (LD1) and configured to store the data input signal (LD1) during a first state of a first clock signal (CP′); and a slack guard circuit comprising: a delay element (214) having an input coupled to the data input of the first latch (206) and configured to generate, at its output, a delayed data signal (PG1); a gated-input cell (216) having an input coupled to an output of the delay element (214), the gated-input cell (216) being configured to propagate the delayed data signal (PG1) during the first state of the first clock signal (CP′); and a comparator (218) having a first input coupled to a data output of the first latch (206) and a second input coupled to an output of the gated-input cell (216).
Bibliography:Application Number: US201916723069