Integrated Assemblies Having Charge-Trapping Material Arranged in Vertically-Spaced Segments, and Methods of Forming Integrated Assemblies
Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels include conductive wordline material having terminal ends. Charge blocking material is along the terminal ends of the conductive wordline material and has first v...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
11.06.2020
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Subjects | |
Online Access | Get full text |
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