SYSTEMS AND METHODS FOR CONFIGURING PROGRAMMABLE LOGIC DEVICES FOR DEEP LEARNING NETWORKS

• Main Authors: Vasantala, Anusha, Gu, Yongfeng, Venkataramani, Girish, Chen, Wang, Vishwakarma, Purshottam, Zhou, Yuteng, Yogaraj, Bharathi, Patil, Vibha
• Format: Patent
• Language: English
• Published: 14.05.2020
• Subjects: CALCULATING; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Systems and methods may configure a programmable logic device to efficiently run a deep learning (DL) network. Architecture code and algorithmic code may be generated. The architecture code may define convolutional and fully connected processor cores structured to run the layers of a Deep Neural Network (DNN). The processor cores may be interconnected by a First In First Out (FIFO) memory. The architecture code may also define stride-efficient memories for implementing convolution. The algorithmic code may include configuration instructions for running the DNN's layers at the processor cores. The algorithmic code may also include a schedule for executing the configuration instructions on the processor cores, for moving network parameters to the processor cores, and for transferring outputs between the layers.