MEMORY ARBITRATION TECHNIQUES BASED ON LATENCY TOLERANCE

Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller implements a per-bank priority-based arbitration scheme for different types of memory traffic (e.g., with different quality of service parameters). In some embodiments, the memory cont...

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Bibliographic Details
Main Authors Biswas, Sukalpa, Notani, Rakesh L, Hsiung, Kai Lun, Fu, Peter, Liu, Yanzhe, Nukala, Lakshmi Narasimha Murthy, Mathews, Gregory S, Magudilu Vijayaraj, Thejasvi, Keil, Shane J
Format Patent
LanguageEnglish
Published 20.02.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller implements a per-bank priority-based arbitration scheme for different types of memory traffic (e.g., with different quality of service parameters). In some embodiments, the memory controller is configured to provide per-bank overrides to the arbitration scheme based on latency tolerance reported by one or more requesters sending a particular type of memory traffic. Various techniques disclosed herein may improve performance, improve fairness among different types of memory traffic, and/or reduce power consumption.
Bibliography:Application Number: US201816104307