Method and Apparatus for Encoding Quasi-Cyclic Low-Density Parity Check Codes

This disclosure presents a method and the corresponding hardware apparatus for encoding low-density parity check codes whose parity check matrices are composed of circulant blocks. The encoder operates on a parity check matrix of a judiciously designed block structure, which permits low cost hardwar...

Full description

Saved in:
Bibliographic Details
Main Authors Reynwar, Benedict J, Declercq, David, Vasic, Bane
Format Patent
LanguageEnglish
Published 06.02.2020
Subjects
BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRICITY
Online AccessGet full text

Cover

More Information
Summary:This disclosure presents a method and the corresponding hardware apparatus for encoding low-density parity check codes whose parity check matrices are composed of circulant blocks. The encoder operates on a parity check matrix of a judiciously designed block structure, which permits low cost hardware implementation, and high encoding throughput.
Bibliography:Application Number: US201916530944