DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBSTRATE

Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant ("low-κ") material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of...

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Bibliographic Details
Main Authors Guler, Leonard, Kang, Jun Sung, Beattie, Bruce E, Guha, Biswajeet, Hsu, William
Format Patent
LanguageEnglish
Published 26.12.2019
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant ("low-κ") material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.
Bibliography:Application Number: US201816015404