REAL-TIME ARBITRATION OF SHARED RESOURCES IN A MULTI-MASTER COMMUNICATION AND CONTROL SYSTEM

A spinlock circuit connected to one or more first processors through one or more broadside interfaces. The spinlock circuit is configured to receive a plurality of requests for use of a computing resource from one or more first processors, and reply to each of the plurality of requests within a sing...

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Bibliographic Details
Main Authors LEYRER, Thomas Anton, WALLACE, William Cronin
Format Patent
LanguageEnglish
Published 05.12.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A spinlock circuit connected to one or more first processors through one or more broadside interfaces. The spinlock circuit is configured to receive a plurality of requests for use of a computing resource from one or more first processors, and reply to each of the plurality of requests within a single clock cycle of the one or more first processors. The spinlock circuit can reply to each of the plurality of requests within a single clock cycle of the one or more first processors by alternately assigning the computing resource to a requesting processor from among the one or more first processors or indicating to the requesting processor from among the one or more first processors that the computing resource is not available.
Bibliography:Application Number: US201916424667