SPLIT-GATE FLASH MEMORY, METHOD OF FABRICATING SAME AND METHOD FOR CONTROL THEREOF

A split-gate flash memory, a method of fabricating the split-gate flash memory and a method for control thereof are disclosed. The split-gate flash memory includes: a semiconductor substrate including a first memory region and a second memory region that are separate from each other; and a word-line...

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Bibliographic Details
Main Author LIU, Xianzhou
Format Patent
LanguageEnglish
Published 21.11.2019
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:A split-gate flash memory, a method of fabricating the split-gate flash memory and a method for control thereof are disclosed. The split-gate flash memory includes: a semiconductor substrate including a first memory region and a second memory region that are separate from each other; and a word-line structure between the first memory region and the second memory region. The word-line structure includes, stacked on the surface of the semiconductor substrate sequentially from bottom to top, a word-line oxide layer, a read gate, a dielectric oxide layer and an erase gate. The read and erase gates can each function as a word line of the split-gate flash memory for enabling a read or erase operation. During the erase operation, a voltage applied on the erase gate has an insignificant impact on the underlying semiconductor substrate, which is helpful in reducing channel leakage in the semiconductor substrate.
Bibliography:Application Number: US201816232487