TRANSLATION OF VIRTUAL ADDRESSES TO PHYSICAL ADDRESSES

A memory management unit (MMU) is disclosed. The MMU is configured to receive a translation request from a processing system, wherein the translation request specifies a virtual address to be translated, search a page table stored in a physical memory system for a page table entry that specifies the...

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Bibliographic Details
Main Authors NORMAN, Jason, SADAYAN EBRAMSAH MO ABDUL, Sadayan Ghows Ghani, PATEL, Piyush, ANIGUNDI, Rakesh
Format Patent
LanguageEnglish
Published 31.10.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A memory management unit (MMU) is disclosed. The MMU is configured to receive a translation request from a processing system, wherein the translation request specifies a virtual address to be translated, search a page table stored in a physical memory system for a page table entry that specifies the virtual address, receive a translation lookaside buffer invalidation (TLBI) signal from the processing system, wherein the TLBI signal specifies the virtual address, in response to receiving the TLBI signal specifying the virtual address, invalidate a translation lookaside buffer (TLB) entry in a TLB, wherein the invalidated TLB entry specifies the virtual address and restart the search of the page table for the page table entry that specifies the virtual address.
Bibliography:Application Number: US201815964061