METHOD AND APPARATUS FOR OBFUSCATING AN INTEGRATED CIRCUIT WITH CAMOUFLAGED GATES AND LOGIC ENCRYPTION

A method and apparatus for obfuscating at least a portion of an integrated circuit is disclosed. In one embodiment, the method comprises computing a number of observable points (COP) for each net of the portion of the integrated circuit, computing a selection weight (WS) for each net, and selecting...

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Bibliographic Details
Main Authors Chow, Lap Wai, Wang, Bryan J, Cocchi, Ronald P, Baukus, James P
Format Patent
LanguageEnglish
Published 22.08.2019
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:A method and apparatus for obfuscating at least a portion of an integrated circuit is disclosed. In one embodiment, the method comprises computing a number of observable points (COP) for each net of the portion of the integrated circuit, computing a selection weight (WS) for each net, and selecting one or more nets for insertion of at least one protection element based on the computed selection weights (WS).
Bibliography:Application Number: US201716333589