MEMORY DEVICE, MEMORY ADDRESS DECODER, SYSTEM, AND RELATED METHOD FOR MEMORY ATTACK DETECTION
A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding path configured to generate a select signal from an input address signal, and fault detecting logic oper...
Saved in:
Main Authors | , , |
---|---|
Format | Patent |
Language | English |
Published |
25.07.2019
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding path configured to generate a select signal from an input address signal, and fault detecting logic operably coupled with the memory decoder and configured to receive feedback signals distributed from the multiple stages indicative of a fault along the decoding path. |
---|---|
Bibliography: | Application Number: US201815956526 |