PREFETCHING WRITE PERMISSIONS INTO ADDRESS TRANSLATION CACHE

Systems, methods, and devices can include circuitry or computer program products to receive a memory address translation request message from a downstream connected device; identify, from the memory address translation request message, a permission indication that the device intends to perform a wri...

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Bibliographic Details
Main Authors Petrica, Paula, Vakharwala, Rupin H
Format Patent
LanguageEnglish
Published 18.07.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Systems, methods, and devices can include circuitry or computer program products to receive a memory address translation request message from a downstream connected device; identify, from the memory address translation request message, a permission indication that the device intends to perform a write access to one or more memory address locations specified in the memory address translation request message; identify, from an address translation and protection table (ATPT), a dirty bit value associated with the one or more memory address locations; and transmit a translation of the one or more memory address locations and a read or read+write permission to the device based on the permission indication in the memory address translation request message and the dirty bit.
Bibliography:Application Number: US201916361512