Twin Bit Non-volatile Memory Cells With Floating Gates In Substrate Trenches

• Main Authors: Wang, Chunming, Liu, Xian, Liu, Andy, Diao, Melvin, Xing, Leo, Do, Nhan
• Format: Patent
• Language: English
• Published: 11.07.2019
• Subjects: ELECTRICITY

A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.