SIMULATING A SINGLE DATA RATE (SDR) MODE ON A DUAL DATA RATE (DDR) MEMORY CONTROLLER FOR CALIBRATING DDR MEMORY COARSE ALIGNMENT

A double data rate (DDR) memory controller writes a test pattern to a location in a DDR memory for a coarse calibration test, delayed by a first number of cycles set in a tunable write delay setting. The DDR memory controller simulates a single data rate (SDR) mode for the coarse calibration test by...

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Bibliographic Details
Main Authors GLANCY, STEPHEN, KING, RYAN P, BIALAS, JR., JOHN S
Format Patent
LanguageEnglish
Published 11.07.2019
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A double data rate (DDR) memory controller writes a test pattern to a location in a DDR memory for a coarse calibration test, delayed by a first number of cycles set in a tunable write delay setting. The DDR memory controller simulates a single data rate (SDR) mode for the coarse calibration test by only comparing every other read beat of the test pattern read from the DDR memory, delayed by a second number of cycles set in tunable read delay setting, wherein every other read beat is latched for a full cycle. The DDR memory controller, responsive to every other read beat of the test pattern matching an expected result, sets the first number of cycles and the second number of cycles as coarse calibration settings for a DRAM.
Bibliography:Application Number: US201815869008