CHECKPOINTING OF ARCHITECTURAL STATE FOR IN ORDER PROCESSING CIRCUITRY

An in-order processor has a mapping storage element to store current register mapping information identifying, for each of two or more architectural register specifiers, which physical register specifies valid data for that architectural register specifier. At least one checkpoint storage element st...

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Bibliographic Details
Main Authors BURGESS, Neil, EISEN, Lee Evan
Format Patent
LanguageEnglish
Published 11.07.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:An in-order processor has a mapping storage element to store current register mapping information identifying, for each of two or more architectural register specifiers, which physical register specifies valid data for that architectural register specifier. At least one checkpoint storage element stores checkpoint register mapping corresponding to a checkpoint of previous architectural state. This enables checkpoints to be saved and restored simply by transferring mapping information between the mapping and checkpoint storage elements, rather than transferring the actual state data.
Bibliography:Application Number: US201815862728