FINE DELAY STRUCTURE WITH PROGRAMMABLE DELAY RANGES

A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and...

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Bibliographic Details
Main Authors Yuan, Xiaobin, Tran, Hung H, Prasad, Mangal, Tiner, Marshall D
Format Patent
LanguageEnglish
Published 20.06.2019
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.
Bibliography:Application Number: US201916284257