Heterojunction Field Effect Transistor Device with Serially Connected Enhancement Mode and Depletion Mode Gate Regions

• Main Authors: de Almeida Braga, Nelson, Wong, Hiu Yung, Mickevicius, Rimvydas
• Format: Patent
• Language: English
• Published: 16.05.2019
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Roughly described, a heterojunction field effect transistor device includes a first piezoelectric layer supporting a channel region, a second piezoelectric layer over the first, and a source and drain. A dielectric layer over the second piezoelectric layer electrically separates the source and drain, and has a plurality of segments, two of them separated by a first gap. A first gate has a first tine, the first tine within the first gap, the first gap having a length of less than about 200 nm. In the first piezoelectric layer immediately beneath the second piezoelectric layer, directly beneath the first gap, stress in the dielectric layer creates a piezoelectric charge of at least about 1×1011 per cm2 of electronic charge. The first gate controls a normally off segment of the channel region. A second gate, having a length of at least 500 nm, controls a normally on segment of the channel region.