Integrated Resistor for Semiconductor Device

A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate...

Full description

Saved in:
Bibliographic Details
Main Authors Kudymov, Alexey, Ramdani, Jamal
Format Patent
LanguageEnglish
Published 28.03.2019
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.
Bibliography:Application Number: US201616081012