INTERLEAVING SCHEME FOR INCREASING OPERATING EFFICIENCY DURING HIGH CURRENT EVENTS ON AN INTEGRATED CIRCUIT

An integrated circuit configured to execute multiple operations in parallel is provided. The integrated circuit may be organized into multiple logic sectors. Two or more groups of logic sectors may be executed in an interleaved fashion, where successive groups of logic sectors are activated after a...

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Bibliographic Details
Main Authors Srinivasan, Archanna, Tan, Jun Pin, Chen, Guang
Format Patent
LanguageEnglish
Published 07.02.2019
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
INFORMATION STORAGE
PHYSICS
PULSE TECHNIQUE
STATIC STORES
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Summary:An integrated circuit configured to execute multiple operations in parallel is provided. The integrated circuit may be organized into multiple logic sectors. Two or more groups of logic sectors may be executed in an interleaved fashion, where successive groups of logic sectors are activated after a predetermined amount of delay. The integrated circuit may include an array of memory cells. Rows of the memory cells may be accessed in an interleaving manner, where successive rows of memory cells are selected after a predetermined amount of delay. Operating groups of circuit components using an interleaving scheme can help improve operational efficiency while reducing power supply noise without having to increase die area for on-die decoupling capacitance.
Bibliography:Application Number: US201715852814