MATRIX MULTIPLICATION ACCELERATION OF SPARSE MATRICES USING COLUMN FOLDING AND SQUEEZING

Disclosed embodiments relate to sparse matrix multiplication (SMM) acceleration using column folding and squeezing. In one example, a processor, in response to a SMM instruction having fields to specify locations of first, second, and output matrices, the second matrix being a sparse matrix, uses ex...

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Bibliographic Details
Main Authors AZIZI, Omid, BOUDOUKH, Guy, ROTZIN, Michael, KOREN, Chen, WERNER, Tony, NURVITADHI, Eriko, YANG, Andrew
Format Patent
LanguageEnglish
Published 07.02.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Disclosed embodiments relate to sparse matrix multiplication (SMM) acceleration using column folding and squeezing. In one example, a processor, in response to a SMM instruction having fields to specify locations of first, second, and output matrices, the second matrix being a sparse matrix, uses execution circuitry to pack the second matrix by replacing one or more zero-valued elements with non-zero elements yet to be processed, each of the replaced elements further including a field to identify its logical position within the second matrix, and, the execution circuitry further to, for each non-zero element at row M and column K of the specified first matrix, generate a product of the element and each corresponding non-zero element at row K, column N of the packed second matrix, and accumulate each generated product with a previous value of a corresponding element at row M and column N of the specified output matrix.
Bibliography:Application Number: US201816016278