Mixed P/N MOS Array Layout and Methods of Forming the Same
A semiconductor structure is disclosed that includes a p-channel metal-oxide semiconductor (PMOS) array having a first set of oxide diffusion layer (OD) structures, an n-channel metal-oxide semiconductor (NMOS) array having a second set of OD structures, and a dummy buffer zone surrounding the PMOS...
Saved in:
Main Authors | , |
---|---|
Format | Patent |
Language | English |
Published |
03.01.2019
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | A semiconductor structure is disclosed that includes a p-channel metal-oxide semiconductor (PMOS) array having a first set of oxide diffusion layer (OD) structures, an n-channel metal-oxide semiconductor (NMOS) array having a second set of OD structures, and a dummy buffer zone surrounding the PMOS and NMOS arrays. The semiconductor structure has a uniform spacing between OD structures in the first and second sets of OD structures and between the PMOS and NMOS array, such that no dummy buffer zone is included between the PMOS array and the NMOS array. |
---|---|
Bibliography: | Application Number: US201715638505 |