SEMICONDUCTOR DEVICE AND FLASH-MEMORY CONTROL METHOD

According to one embodiment, a memory controller is configured so that when the memory controller controls a writing/erasing process for a flash memory performed by a first or second master, the memory controller can prohibit, while the first master is performing the writing/erasing process for the...

Full description

Saved in:
Bibliographic Details
Main Author KURAFUJI, Takashi
Format Patent
LanguageEnglish
Published 27.12.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:According to one embodiment, a memory controller is configured so that when the memory controller controls a writing/erasing process for a flash memory performed by a first or second master, the memory controller can prohibit, while the first master is performing the writing/erasing process for the flash memory, an interruption of the writing/erasing process in execution, the interruption resulting from access to the flash memory by the second master.
Bibliography:Application Number: US201815970083