INTEGRATED CIRCUITS AND PROCESSES FOR PROTECTION OF STANDARD CELL PERFORMANCE FROM CONTEXT EFFECTS

Integrated circuit (5) includes substrate (10) with surface (20) and structure (30) including base levels (45.i, 45.(i+1)), terminating cells (48, 49), and block (40) of standard cells arranged in rows (42.i, 42.(i+1)), and another type of block (60) outside block (40). Standard cells at at least tw...

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Bibliographic Details
Main Authors Aton, Thomas J, Terry, Roger Mark, Pitts, Robert L
Format Patent
LanguageEnglish
Published 29.11.2018
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:Integrated circuit (5) includes substrate (10) with surface (20) and structure (30) including base levels (45.i, 45.(i+1)), terminating cells (48, 49), and block (40) of standard cells arranged in rows (42.i, 42.(i+1)), and another type of block (60) outside block (40). Standard cells at at least two edges of block (40) have the following protections: (1) block (60) has strip of separation (41.j) having at least a minimum width from the edges of block (40), and protected by one of the following: (2) terminating cells (48, 49) reduce context effect and some terminating cells (48) are placed at at least one end of rows (42.i, 42.(i+1)) of standard cells within first-named block (40), and (3) the terminating cells (48, 49) reduce context effect and some terminating cells (49) are at one end of a column of standard cells within block (40). Other structures, devices, and processes are also disclosed.
Bibliography:Application Number: US201816052770