SCALABLE PACKAGE ARCHITECTURE AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS

• Main Authors: Nimkar, Nitesh, Ganesan, Sanka, Ziadeh, Bassam
• Format: Patent
• Language: English
• Published: 15.11.2018
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.