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Summary:A signal generation circuit, a voltage conversion device, and a computer program are provided wherein the minimum increment of a value to be set for a generating portion, can be made substantially smaller than an actual increment with a relatively small processing load. A CPU specifies a set value Y (closest to a target value X) and a second closest set value Z in every N periods of a first signal, determines N set values for the first signal by combining Y and Z based on the result of comparison between the values of Y and Z and the value of X, sets one set value for a generating portion for each period of the first signal, calculates a value for setting off-time of the second signal in a first period in N periods as an additional value, and sets the calculated value for the generating portion.
Bibliography:Application Number: US201615767418