3D VERTICAL FET WITH TOP AND BOTTOM GATE CONTACTS

• Main Authors: Anderson, Brent A, Chu, Albert M
• Format: Patent
• Language: English
• Published: 25.10.2018
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method for forming a semiconductor device includes forming bottom side metallization structures having at least one connection to a bottom side of a vertical transistor disposed on a substrate, the bottom side metallization structures including a power rail and a ground rail. After forming the bot...