3D VERTICAL FET WITH TOP AND BOTTOM GATE CONTACTS

A method for forming a semiconductor device includes forming bottom side metallization structures having at least one connection to a bottom side of a vertical transistor disposed on a substrate, the bottom side metallization structures including a power rail and a ground rail. After forming the bot...

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Main Authors Anderson, Brent A, Chu, Albert M
Format Patent
LanguageEnglish
Published 25.10.2018
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Abstract A method for forming a semiconductor device includes forming bottom side metallization structures having at least one connection to a bottom side of a vertical transistor disposed on a substrate, the bottom side metallization structures including a power rail and a ground rail. After forming the bottom side metallization structures, the substrate is removed and the vertical transistor is flipped. Top side metallization structures are formed. The top side metallization structures having at least one connection to the vertical transistor on a top side of the vertical transistor.
AbstractList A method for forming a semiconductor device includes forming bottom side metallization structures having at least one connection to a bottom side of a vertical transistor disposed on a substrate, the bottom side metallization structures including a power rail and a ground rail. After forming the bottom side metallization structures, the substrate is removed and the vertical transistor is flipped. Top side metallization structures are formed. The top side metallization structures having at least one connection to the vertical transistor on a top side of the vertical transistor.
Author Chu, Albert M
Anderson, Brent A
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Snippet A method for forming a semiconductor device includes forming bottom side metallization structures having at least one connection to a bottom side of a vertical...
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SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title 3D VERTICAL FET WITH TOP AND BOTTOM GATE CONTACTS
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