LOW RESISTANCE SOURCE/DRAIN CONTACTS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICES

• Main Authors: Guo, Dechao, Venigalla, Rajasekhar, Gluschenkov, Oleg, Adusumilli, Praneet, Liu, Zuoguang, Yamashita, Tenko
• Format: Patent
• Language: English
• Published: 13.09.2018
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method for fabricating a semiconductor device includes accessing source/drain regions (S/D) in an n-type field effect transistor (NFET) region and in a p-type field effect transistor (PFET) region. First alloy elements are implanted in the S/D regions in the NFET region, and second alloy elements are implanted in the PFET region with the NFET region blocked. The first and second alloy elements form respective amorphized layers on the S/D regions in respective NFET and PFET regions. The amorphized layers are recrystallized to form metastable recrystallized interfaces using an epitaxy process wherein the metastable recrystallized interfaces formed in respective NFET and PFET regions exceed solubility of the first and second alloy elements in respective materials of the S/D regions in the NFET and PFET regions. Contacts to the metastable recrystallized layers of the S/D regions in the NFET and PFET regions are concurrently formed.