Arithmetic Lazy Flags Representation for Emulation

In aspects of arithmetic lazy flags representation for emulation, a host processor system receives application instructions that are designed for execution by a guest processor system that is different than a processor architecture of the host processor system. A host emulator receives an applicatio...

Full description

Saved in:
Bibliographic Details
Main Author Mihocka, Darek Josip
Format Patent
LanguageEnglish
Published 30.08.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:In aspects of arithmetic lazy flags representation for emulation, a host processor system receives application instructions that are designed for execution by a guest processor system that is different than a processor architecture of the host processor system. A host emulator receives an application instruction that includes an arithmetic operation, determines a result value of the arithmetic operation that is performed on integer values, and determines a first state variable and a second state variable. The host emulator also determines whether a subsequent application instruction will need a derivation of a subset of arithmetic flags based in part on a third state variable. The host emulator can then determine that the subsequent application instruction does not need the derivation of the subset of arithmetic flags, and perform the subsequent application instruction without a determination of the third state variable, thereby reducing processor clock cycles to emulate the application instructions.
Bibliography:Application Number: US201715445403