BANDWIDTH-AWARE MULTI-FREQUENCY PERFORMANCE ESTIMATION MECHANISM

Systems, apparatuses, and methods for implementing performance estimation mechanisms are disclosed. In one embodiment, a computing system includes at least one processor and a memory subsystem. During a characterization phase, the system utilizes a memory intensive workload to detect when the memory...

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Bibliographic Details
Main Authors Piga, Leonardo, Shahneous Bari, Md Abdullah, Paul, Indrani
Format Patent
LanguageEnglish
Published 26.07.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Systems, apparatuses, and methods for implementing performance estimation mechanisms are disclosed. In one embodiment, a computing system includes at least one processor and a memory subsystem. During a characterization phase, the system utilizes a memory intensive workload to detect when the memory subsystem reaches its saturation point. Then, the system collects performance counter values during a sampling phase of a target application to determine the memory bandwidth. If the memory bandwidth is greater than the saturation point, then the system generates a prediction of the memory time which is based on a ratio of the memory bandwidth over the saturation point. Otherwise, if the memory bandwidth is less than the saturation point, the system assumes memory time is constant versus processor frequency. Then, the system uses the memory time and an estimate of the compute time to estimate a phase time for the target application at different processor frequencies.
Bibliography:Application Number: US201715416993