TRANSISTOR STRUCTURE WITH VARIED GATE CROSS-SECTIONAL AREA
Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin in...
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Main Authors | , , , |
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Format | Patent |
Language | English |
Published |
05.07.2018
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Subjects | |
Online Access | Get full text |
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Summary: | Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin. |
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Bibliography: | Application Number: US201815911415 |