METHODS OF DESIGNING A LAYOUT OF A SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME

A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pi...

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Bibliographic Details
Main Authors CHO, SUNGWE, DO, JUNG-HO, BAEK, SANGHOON, SONG, TAEJOONG, YANG, GIYOUNG, LIM, JINYOUNG
Format Patent
LanguageEnglish
Published 21.06.2018
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.
Bibliography:Application Number: US201815896415