INTEGRATED CIRCUIT PROTECTION DURING HIGH-CURRENT ESD TESTING

A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated s...

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Bibliographic Details
Main Authors GAUTHIER, JR. ROBERT J, JACK NATHAN, MITRA SOUVICK, CHANG SHUNHUA, DI SARRO JAMES PAUL
Format Patent
LanguageEnglish
Published 12.04.2018
Subjects
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.
Bibliography:Application Number: US201715834192