DETECTING BUS LOCKING CONDITIONS AND AVOIDING BUS LOCKS
A processor may include a register to store a bus-lock-disable bit and an execution unit to execute instructions. The execution unit may receive an instruction that includes a memory access request. The execution may further determine that the memory access request requires acquiring a bus lock, and...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
01.03.2018
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Subjects | |
Online Access | Get full text |
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Summary: | A processor may include a register to store a bus-lock-disable bit and an execution unit to execute instructions. The execution unit may receive an instruction that includes a memory access request. The execution may further determine that the memory access request requires acquiring a bus lock, and, responsive to detecting that the bus-lock-disable bit indicates that bus locks are disabled, signal a fault to an operating system. |
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Bibliography: | Application Number: US201615251425 |